Lucent offers CSCs as DAI debuts

Lucent offers CSCs as DAI debutsSteve Bush
Lucent Technologies Microelectronics Group is offering two new Customer Solution Cores (CSCs) for high-speed data coms and telecoms functions in its ORCA field-programmable gate arrays (FPGAs).
The cores are pre-coded, pre-tested and pre-verified building blocks that let equipment manufacturers incorporate these functions in their designs thereby reducing the time that must be spent developing ATM systems.
The ATM Physical Layer core provides the ATM cell-based communications protocol and features 155.52-Mbit/s ATM line operation. The UTOPIA core, which provides the UTOPIA interface specification, supports both UTOPIA Level I and II operation at up to 50 MHz.
The ATM Physical Layer core implements the complete ATM physical layer of the ATM User Network Interface specification V.3.1 into an ORCA FPGA. It also integrates the UTOPIA core to provide the ATM Forum’s UTOPIA Level I or II interface to the ATM Layer.
“The inclusion of the Level II interface gives Lucent’s cores three major improvements over cores with Level I alone,” said Lucent spokesperson Sabine Haeseler. “Support for all multi-PHY modes in the UTOPIA II specification, support for both 8-bit and 16-bit bus width, and operation at 25MHz, 33 MHz or 50 MHz.”
Both cores are aimed at manufacturers of ATM test equipment, LAN equipment, and datacoms and telecoms network equipment who are looking for a wider choice of features, such as different interfaces and control logic, than is available in standard, off-the-shelf ATM chips.
Design Acceleration (DAI) is a Californian company that focuses on design verification tools. New to the UK at the Silicon Design Show are a VHDLversion of Signalscan DX, its previously Verilog-only waveform viewing and simulation analysis environment, and an updated version of Coverscan, its Verilog code coverage analysis tool.
Signalscan DX is based around a simulation database called SST2. Signals from this are claimed to load “in a fraction of the time it takes to load a conventional VCD file”. The new version, 5.1, includes the company’s TurboCompression, which is said to store files in 5 to 20 per cent of the space required for a VCD file.
Coverscan, now at version 2.0 and supporting Verilog-XL and equivalents, provides information about which proportions of Verilog HDL code have been exercised during simulation. Analysis with version 2.0, may now be done at module and module-type levels.


Leave a Reply

Your email address will not be published. Required fields are marked *

*