Making an announcement at the Electronica USA tradeshow in San Francisco, IMEC said it has organised a new research programme for a flexible power-efficient architecture and an easy design flow for future wireless and multimedia systems. By combining a VLIW DSP with a coarse-grained array, IMEC has developed a power-efficient flexible architecture template and a retargetable compiler for coarse-grained reconfigurable processors, according to the R&D centre.
The VLIW DSP efficiently executes control-flow code by exploiting instruction-level parallelism, IMEC said. The array, containing many function units, accelerates data-flow loops by exploiting high degrees of loop-level parallelism. The architecture template allows designers to specify the interconnection, type and number of function units.
The C compiler targets both the VLIW processor and the array. Application source code can therefore be compiled directly onto the coarse-grained reconfigurable processor, according to IMEC. This architectural flexibility and C design flow allows a designer to rapidly explore architectural options for an application domain; applications can be programmed completely in C.
IMEC currently has a functioning prototype of the retargetable compiler and is conducting ongoing research in benchmarking the architecture in terms of power, performance and area. Initial results are available for a MPEG-2 decoder mapped on an array of 64 function units, showing a speed improvement of a factor of three over a standard VLIW processor, IMEC said.
Future research will focus on improving the memory hierarchy, developing the control path and a systematic architectural exploration methodology.
is Electronics Weekly’s affiliated US site.