Mentor and Synopsys join on IP integration

Mentor and Synopsys join on IP integration
Richard Ball Mentor Graphics and Synopsys have jointly written a design manual showing companies how to build Asics using a mixture of intellectual property (IP) cores. The manual uses the standards set out by the Virtual Socket Interface (VSI) Alliance, which aims to make designing ICs as simple as building printed circuit boards. “We have developed a joint methodology manual to show how to integrate cores to VSI Alliance standards,” said Wally Rhines, chief executive of Mentor. The motivation for producing the manual is simple: Mentor hopes that companies developing chips will use IP from Inventra, its IP business unit, while Synopsys wants people to use its cell-based array (CBA) library when designing Asics. To prove the concept, IP from Mentor’s Inventra business unit was manufactured using Synopsys’ CBA. “We decided to take the Inventra cores, map them onto CBA and tape them out to check they work,” said Aart de Geus, chairman and CEO of Synopsys. Over 50 cores have gone through this process. Companies that have already embraced the Mentor/Synopsys concept include ARM and STMicroelectronics (ST). “We will use the manual for future designs such as set-top box chipsets,” said an ST spokesperson. In a separate announcement, the two EDA companies agreed to license tools from each other. “We have signed an agreement to cross-license each other’s tools to ensure interoperability,” said de Geus. This, they say, will ensure that their design tools work with those from other companies. “Users’ criticisms say there is not enough interoperability in real world design flows,” said Rhines.


Leave a Reply

Your email address will not be published. Required fields are marked *

*