Motorola gets high on low-k to quicken Ics

Motorola gets high on low-k to quicken Ics
Richard Ball Motorola has developed a technique for combining copper interconnects with a low-k dielectric material which could dramatically increase IC speeds. The company claims it is the first to fabricate multiple layers of metal separated by a porous material. This has proven difficult because the honeycomb-like material has poor thermo-mechanical properties: heat is not readily conducted away and stress causes fractures. Although it refuses to say how the integration is achieved, Motorola claims to have manufactured sections of a PowerPC processor and SRAM using the technique. “In going to increasingly lower dielectric constant materials, we’re reducing the capacitance contribution to RC delays,” said Fabio Pintchovski, director of Motorola’s advanced products R&D lab. “This has the benefit of smaller signal propagation delays, less cross-talk between adjacent lines and reduced power consumption,” he said. The researchers have used materials with a dielectric constant of between 2.0 and 2.5. In comparison, the SiO2 used today has a k value of 3.9 to 4.2. This could halve chip delays due to interconnect, which at 0.18?m and below dominate overall device speeds. Stress levels in the new structures are said to be the same as those in copper/SiO2 devices. Bringing this R&D work to commercial production will take three years, the firm said.


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