NEC has announced an Asic process featuring drawn gate lengths of 0.18 and 0.15?m.

NEC has announced an Asic process featuring drawn gate lengths of 0.18 and 0.15?m.
Richard Ball The CB-11 process aims to integrate high speed logic and dense memory on chips running at up to 500MHz. A modular process allows the standard CMOS logic to be placed on the same die as DRAM and Flash memory. Analogue components and BiCMOS transistors can also be implemented. In order to develop complete system-on-a-chip Asics, NEC is offering a range of intellectual property (IP) cores and macros. IP includes microprocessors, digital signal processors and memory. Large scale macros include phase locked loops, Firewire bus, accelerated graphics port and digital subscriber line cores. The 0.18?m process can integrate up to 34 million gates. An internal voltage of 1.8V results in power consumption of 15nW/MHz/gate. The smaller process is limited to 22 million gates and has slightly higher power consumption, but the speed of an inverter is halved from 17 to 8.5 picoseconds. NEC will start accepting designs in the process this June. Samples will be available in December with full production early next year, the company said.


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