NEC/Toshiba to cut Rambus DRAM cost with 0.2?m process

NEC/Toshiba to cut Rambus DRAM cost with 0.2?m process
Richard Ball In a move to bring down costs of Rambus DRAMs, NEC and Toshiba have announced 128Mbit parts that will be made in a 0.20?m process. Today’s leading edge DRAM processes are running at 0.22?m. “We’re using 0.22?m right now,” said an NEC spokesperson. “We will probably shift to 0.20?m before going to mass production.” The shift is an attempt to reduce costs by shrinking the Rambus DRAMs, which are between ten and 20 per cent larger than their synchronous counterparts. “Larger dies mean more trouble in packaging, and a smaller area enhances performance and lowers cost,” the NEC spokesperson said. NEC’s shift to 0.20?m reduces the die size from 130mm2 to 105mm2. It also makes it easier to reach the target speed of 800Mbit/s per pin. Toshiba’s 128Mbit part uses 103mm2 of silicon, the firm said. It has also announced a 144Mbit device, the extra bits to support error correcting code. The die measures 114mm2. Both firms expect to be in volume production when Intel’s Camino chipset, supporting Rambus, is available later this year. A 128Mbit Rambus DRAM is expected to cost around $25 when firms start volume production later this year.


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