Newcomer speeds up mixed-signal chip design

Newcomer speeds up mixed-signal chip design
Richard Ball Antrim Design Systems, a newcomer to the EDA world, has announced a simulation tool for mixed-signal chip designs. “We talked to 40 different companies around the world about their problems in mixed-signal design,” said Les Spruiell, v-p of marketing. Engineers pointed out that tools for the analogue side of design are highly manual and work at too low a level. While designing a digital block can take six to eight weeks, the analogue portion of the design can take as many months, Spruiell said. The problem is that simulation is often not done until the analogue portion is laid out. Iterations are therefore slow. Antrim has made use of the analogue and mixed-signal extensions to the Verilog hard description language (HDL). Verilog-AMS allows an entire mixed-signal chip to be represented as an HDL. The simulator, dubbed Antrim-A/MS, contains several algorithms for simulating different mixed-signal circuit types. “The simulation performance is incredible. We’re six to eight times faster than the competition,” said Spruiell.


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