Next Generation Sony Playstation Chip detailed at ISSCC

Next Generation Sony Playstation Chip detailed at ISSCC
Steve Bush in San Francisco
Sony Computer Entertainment has used the International Solid State Circuit Conference (ISSCC) to detail its next generation Sony Playstation CPU.
The 10.5 million transistor IC, co-developed with Toshiba, comprises a MIPS processor CPU, a floating point co-processor, two floating point vector units and an MPEG-2 decoder.
The CPU is a two-instruction superscalar design with 128-bit wide internal registers.
The chip has a total of ten floating point multiply/accumulators (MACs) and four floating point dividers. Its processing performance includes four MAC operations per clock cycle, while a 4×4 matrix by 4×1 vector multiplication takes four cycles.
Clocked at 250MHz and operated at 1.8V, the device’s estimated power consumption is 15W.
Asked whether the chip will be in the next Sony Playstation, one of the paper’s authors, Sony’s Masakazu Suzuoki would not be drawn. “I cannot discuss commercial aspects,” he said. However, an ISSCC press release confirmed its intended use.


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