Packaging plays major chip role

Packaging plays major chip role
David Manners Clever packaging is going to be the key differentiator in future chip generations. So claims Dr Tsugio Makimoto, senior executive managing director of Hitachi’s Semiconductor division which is sampling the first 256Mbyte DIMMs, allowing the maximum 1Gbyte of memory on four-slot Intel-type motherboards. “We have been in discussions with Intel about our 256Mbyte DIMM based on our stacked tape carrier packaging technology which we are now sampling,” says Makimoto. “It’s the only way to make a 256Mbyte DIMM.” The 256Mbyte, 168 pin, 32M-word by 72-bit, two-bank, PC100-compliant module, uses 36 64Mbit DRAMs stacked back-to-back. It is needed by the workstation and server manufacturers. “Packaging is becoming very important for achieving higher density at the systems level,” added Makimoto. Agreeing with Makimoto, Walter Roessger, v-p for Europe of the equipment manufacturers’ trade body SEMI, asked EW: “How are you going to use complicated, system level chips driven by very high frequencies – like 700MHz – without very clever packaging? The old idea that semiconductor costs split 80 per cent front end and 20 per cent back end is going to change.”


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