Programmable logic tool boost

Programmable logic tool boost
Richard Ball Synplicity, the programmable logic synthesis company, has updated Synplify, its flagship tool, with new synthesis algorithms and improved timing constraints giving shorter design times. “Newer FPGAs are really big and wiring delays are becoming significant as with Asics,” said Jeff Garrison, product marketing manager. “Place and route runtimes have become a bottleneck.” On a large design, the place and route can take several times longer to complete than the synthesis. So the company has introduced more options for timing constraints during synthesis. Two options help the synthesis tool with critical path optimisation and routeing without overly constraining the place and route tool. Synplify has added new algorithms for synthesis. Rather than shift from VHDL or Verilog directly to gates during synthesis, Synplify maintains behavioural links between the design’s sections. This, Garrison said, allows the tool to make better global optimisations, improving performance and limiting the area used for the final design.


Leave a Reply

Your email address will not be published. Required fields are marked *

*