Show report – Lexra dedicates MIPS' DSP core

Show report – Lexra dedicates MIPS’ DSP coreRichard Ball
Lexra announced the LX5280 at the Embedded Processor Forum, a core aimed at pushing the MIPS Technologies’ architecture into the realm of dedicated DSPchips.
“The LX5280 has been developed specifically for IP licensing. It’s based on the MIPS Risc architecture, but has been extended for specific DSPapplications,” Pat Hays, Lexra’s vice-president and chief technology officer, told Electronics Weekly.
Intended applications are in communications, such as mobile phones and basestations, modems and IP telephony.
The chip is based on the firm’s LX4180, a five stage pipeline Risc processor that uses the MIPS I instruction set. Added to this is a dual issue, superscalar DSP.
“Superscalar is not good for Risc because of the extra area, but on a DSP you can get 80 per cent better performance from a dual system,” Hays said.
“The Risc datapath is 32-bits, but this is overkill for most DSPapplications,” he said. Therefore the DSP unit executes two parallel 16-bit multiply accumulates (MACs) per clock cycle. There is a latency of two cycles, but sustained throughput is two MACs per cycle.
“However, sustaining two 16-bit MACs presents some bandwidth problems,” Hays pointed out. So Lexra has added a second 32-bit data bus to load the four 16-bit operands in a single cycle.
The MAC has a saturation bit, handles fractional or integer arithmetic and has rounding modes.
“We’ve added what we think is a minimum set of extensions, to keep within the spirit of a Risc processor,” Hays said.
When optimised for performance, the core will run at 200MHz in a 0.18?m, 1.8V process. Power dissipation is claimed to be 225mW, worst case, or 1.1mW/MHz.
This is very aggressive considering the 400 million MAC/s that are available at 200MHz. “Performance is quite comparable to TI’s benchmarks for the C62x,” claimed Hays.
If overall power consumption is more important, a 1V version will clock at 50MHz using just 20mW.
In either case – power or performance – the core occupies under 6mm2 of silicon, without caches or other RAM.
Like ARM, Lexra will be offering the processor core in both a soft, synthesisable version and a hard macro.
The synthesisable version of the LX5280 will be available in November, said Hays. Hard macros in GDS II format will be available for most of the commercial foundries in February next year.


Leave a Reply

Your email address will not be published. Required fields are marked *

*