Show report – ST100 core offers best of both DSP and micro worlds

Show report – ST100 core offers best of both DSP and micro worldsRoy Rubinstein
The vision of a single processor for mobile handsets has moved a step closer with the launch of STMicroelectronics’ ST100 DSP core.
“There are not two worlds – the microcontroller and the DSP – anymore,” said Didier Fuin, STMicroelectronics’ (ST) chief architect of the ST100 which combines the Risc instructions of a microcontroller with a DSP.
Fuin does not believe that the ST100 will immediately usurp the role of the microcontroller in a handset design. After all, too much investment has been made by companies in the controller software. “But the core could do the two roles”, he said.
The ST100 – like the recently announced StarCore architecture from Lucent Technologies and Motorola – is being targeted at both high end applications and the low power, high code density markets. STMicroelectronics vs Lucent/Motorola   ST’s ST100 StarCore SC140 Device DSP/microcontroller DSP Architecture 32-bit/dual-MAC 16-bit/quad-MAC Clock 300MHz/100MHz 300MHz Operating voltages 1.8V/1.0V 1.5V/0.9V  
Where it differs from the first announced StarCore, the SC140, is that the ST100 has two multiply/accumulate (MAC) units rather than four. Clocked at 300MHz and with an operating voltage of 1.8V, the ST100 achieves 600MMAC/s. For lower power, handheld applications 200MMAC/s is possible with the operating voltage reduced to 1.0V and the clock down to 100MHz.
The ST100 is classed as a 32-bit architecture yet is described by Fuin as having three instructions lengths: 16-, 32- and 128-bit long. The core’s 16-bit instructions are the microcontroller Risc ones, the 32-bit instructions enable more complex DSP arithmetic and overcome the bit field limitation of the compact 16-bit instructions, while the 128-bit long instructions – four 32-bit words – handle the vector operations required when executing DSP algorithms.
This may sound complicated but Fuin stressed that it offers the best of both the DSPand microcontroller worlds. It ensures high code densities by using the short instructions for the control functions that make up the bulk of the code, while being computationally efficient for the critical DSP processing which attracts most of the core’s attention.
ST calls the 128-bit instructions scoreboarded long instruction words (SLIW). Unlike the very long instruction word DSParchitectures where the compiler identifies data dependencies, SLIW performs the task in hardware. The advantage of SLIW is a greater code density and the hiding of memory latencies, said Fuin, although it does require additional gates.
The ST100 is also claimed to come with a highly efficient C compiler, typically needing only ten per cent of the code to be fine-tuned in assembler.
ST is already working with one customer to use the core in a mobile handset design. It expects first silicon by the year end. Meanwhile, the software tools – such as the ST100 simulator – will be available from the third quarter onwards.

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