SIA report predicts 0.13?m 'year early'

SIA report predicts 0.13?m ‘year early’
Richard Ball The Semiconductor Industry Association (SIA) says that a 0.13?m semiconductor manufacturing process will be in mainstream use by 2002, a year earlier than expected. The prediction has resulted in the SIA dropping the 0.15?m manufacturing process from its roadmap. Looking ahead, the SIA predicts that by 2014, chips will be manufactured using 35nm (0.035?m) design rules, with as many as ten layers of metal, presumably copper. Such a process will be capable of forging Terabit DRAMs, while logic ICs will squeeze nearly 400 million transistors into a square centimetre. By then 450mm (18 inch) wafers will be used. More immediately, the report says Gigabit DRAMs will be available in samples by the year end, with volume production beginning in 2000. This year will also see leading edge designs using on-chip clocks running at 1.25GHz. Packaging costs have also been revised. The SIA states that the cost per pin ranges from $0.70 to $2.52. This is a 40 per cent reduction at the lower end over previous estimates. Chip scale devices today cost $0.90/pin to package. The SIA stresses there are several challenges in achieving higher chip integration, not least of which is the issue of lithography. According to the SIA, an industry-wide consensus is needed as to what will replace optical lithography for processes smaller than 130nm.


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