Smaller than a DRAM, but fast as an SRAM

Smaller than a DRAM, but fast as an SRAMJoint Hitachi/Cambridge University project heralds in a new era of memory, says Richard Ball
A memory device that could replace DRAM, flash and possibly SRAM has been developed by Hitachi and Cambridge University researchers.
Called PLEDM, or phase-state low electron-number drive memory, it is half the size of DRAM, yet is non-volatile and can be made as fast as SRAM.
“Its area is half that of DRAM and is smaller vertically and simpler to manufacture,” said Dr. David Williams at the Hitachi Cambridge Labs.
PLED memory uses standard silicon processes to manufacture, in ten per cent fewer steps than DRAM. Its similarity to CMOS makes it easier to integrate with logic. “It’s called a gain cell structure which has an ordinary MOSFET as the base,” said Williams.
In the position the MOSFET’s gate would normally occupy sits the second PLED transistor, but stacked vertically. The drain is at the bottom, the source at the top, with its gate on the side.
Because the PLED transistor is vertical, it can be manufactured in place of the MOSFET’s gate with standard silicon processing.
“When the stacked transistor is turned on, charge can flow in or out of the drain region, either adding or removing electrons from the gate of the MOSFET,” said Williams.
In a memory cell, the word line switches the gate, while the bit line is attached to the source.
When the transistor is switched off, electrons (or lack of) are trapped in the MOSFET’s gate region, storing one or zero.
Each individual cell has a read/write time of 1ns, but when integrated in a chip will have times of tens of nanoseconds – comparable to DRAM.
Apart from non-volatility, size and ease of manufacture, PLEDM has other advantages over DRAM.
“There are several problems with DRAM,” said Williams. “It’s difficult to scale significantly in terms of size and electrons per bit.”
The latter, electrons/bit, is a major problem. A DRAM cell has no inherent amplification, so signal to noise ratio is critical, and a large number of electrons are needed. Electrons/bit, currently standing at about 5×10 5 , has not scaled down as the size of the DRAM cell has reduced.
“In the PLED structure, using the same silicon procedures, you use about 10 3 electrons/bit,” claimed Williams. “That’s a big advance and is good for speed and power consumption.”
So moving to the PLED structure also eases manufacturing by removing the need for large capacitors to store the half million electrons in a DRAM cell.
As process technology gets smaller, the number of electrons/bit will continue to fall. At the 64Gbit stage, in around 2010, PLEDMs will be using about 50 electrons/bit, while DRAM will still be at 10 5 . SimLED… Although it may not look simpler, the PLED memory is smaller than the conventional one-transistor, one-capacitor memory used today. The PLED transistor sits vertically on top of the Mosfet, needing no further silicon area. The DRAM’s capacitor is large and needs horizontal and vertical space. Unlike flash a PLEDM has no limit on the number of erase/write cycles.


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