Speed is not the only factor to dictate processing performance

Speed is not the only factor to dictate processing performanceRoy Rubinstein  
 
What are the key parameters that dictate the processing performance of silicon?
Theo Claasen used his keynote address to dispel the myth the computational performance is primarily an issue of device clock speed. For Philips Semiconductors’ chief technology officer what dictates the ‘strength’ of silicon is an altogether more subtle subject.
Starting with computational performance, Claasen showed how microprocessor benchmark SPECint figures are doubling every two years. SPECint, which involve running representative algorithms, is a more appropriate way of gauging device processing performance than the traditional million of instructions or million of operations per second (MOPS)measures. This is because instructions differ in the number of operations they perform, not all of which contribute to the computation.
Claasen then tackled the issue of power dissipation, highlighting its inexorable rise with processing performance. According to the Semiconductor Industry Association’s roadmap, by the year 2012 devices will have an operating voltage of 0.6V and consume 175W. Hence power dissipation will become the key cost issue, overtaking silicon area considerations.
For these reasons Claasen argues that computational efficiency – the ratio of processing performance against power – is an overall more insightful measure.
The evolving nature of computational silicon further complicates the picture. Microprocessors are traditionally suited to data processing whereas DSPs are more efficient at handling signal processing tasks in terms of power dissipation and chip area. However, this difference is becoming blurred with media processors capable of tackling both styles of computing.
For more explicitly defined applications a different hardware/ software trade-off is possible. Programmable architectures can be tailored to achieve greater computational efficiency. This efficiency is at the expense of flexibility but now all the operations contribute to the computation. The ‘strength’ of a silicon can now be meaningfully measured using MOPS/W, what Claasen calls the “intrinsic computational efficiency of silicon”.
Achieving flexibility and cost efficiency thus requires elements from both worlds. Flexibility implies software running on programmable cores while tasks which are inefficient in software should be mapped onto co-processor units, said Claasen.
This has led to the emergence of multi-core ‘silicon system platforms’ such as set-top boxes and mobile phone chips.
With the develop of digital TV, Internet and video enabled handsets, computing power and transmission capacity will continue to grow exponentially. Only by concentrating on the intrinsic computational efficiency of silicon will designs be realised with manageable chip areas and power dissipations.
“Speed [clock speed] will remain important, but it is not the only parameter to be pushed to the limits,” said Claasen.


Leave a Reply

Your email address will not be published. Required fields are marked *

*