Starcore aims for the highs and lows of the DSP market

Starcore aims for the highs and lows of the DSP marketAs companies look to strengthen their intellectual property portfolio Lucent Technologies and Motorola have linked up to produce the StarCore SC140 core which performs 1.2GMAC/s at 300MHz. Roy Rubenstein
One result of the prolonged downturn afflicting the semiconductor industry has been a rethink by several leading chip firms. Companies are recognising that their future well-being is directly linked to the strength of their intellectual property (IP) portfolio. This has led to an increased focus on chip design at the expense of chip manufacturing.
One way to develop IPwhile reducing the investment required is through alliances. One of the more surprising ones was last year’s link up between former DSP rivals Lucent Technologies and Motorola .
The two companies pooled their DSP resources to set up the StarCore design centre, tasked with developing a scalable DSP architecture for use in both companies’ next generation of products. Ten months on and the first core has been unveiled.
The StarCore SC140 core, the first in the SC100 family, is distinctive in that it is being targeted at both the high-end and the low power, high code density markets. Competing DSP firms such as Analog Devices – with its TigerSharc and ADSP-218x/9x DSPs – and Texas Instruments (TI) – with its TMS320C6000 and C5000 families – address the two segments with distinct architectures.
To spread one architecture across a range of requirements has required some design ingenuity. To tackle the high performance market such as multi-channel basestation and modem banks, the SC140 core features four multiply/accumulate (MAC) units and four arithmetic/logic units – a DSP first. This equates to a peak processing performance of 1.2GMAC/s when the core is clocked at 300MHz. To feed such a processing rate the core has two 64-bit-wide data buses, to achieve a total data bandwidth of 4.8Gbyte/s.
The core also uses a variable instruction length scheme to improve overall code density, an important factor which dictates a design’s memory requirement. The scheme allows a single 16-bit instructions to be used for control functions, which accounts for the bulk of the code, while for the remaining short but critical inner loops, up to six instructions per clock cycle – four MACs and two data moves – are issued (see diagram).
The core is also programmable in C, requiring a limited amount of code optimisation at the assembler level, claims Thomas Brooks, StarCore’s marketing director.
The SC140 core also boasts a low power consumption. At the 1.5V operating voltage, 0.44mA is required for a quad MAC, equating to a drawn current of 0.11mA/Mip. Operated at 0.9V, the current drawn reduces to 0.07mA/Mip.
Motorola and Lucent will use the SC100 cores in system ICs targeted at applications such as cellular basestations, handsets and digital subscriber line modems. A 300MHz SC140 based IC is expected to be able to handle over 32 enhanced full rate GSMspeech channels in a basestation application.
At first glance the need for a 1.2GMAC/s DSP in a handset is less obvious, especially when current GSMhandsets require a 100Mips DSP. However, for third generation handsets running GPS and full video sequences, a step-function jump in processing performance is expected. “Thousands of Mips will be needed,” says Brooks.
First samples of the SC140 are expected by the year end.


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