StarCore DSP performs 1.2GMAC/s at 300MHz

StarCore DSP performs 1.2GMAC/s at 300MHz
Roy Rubenstein StarCore, the joint venture between Motorola and Lucent Technologies, has upped the DSP ante with the launch of its first core. The firm claims it is the first DSP architecture to have four multiply/accumulate (MAC) units, equating to a peak processing performance of 1.2GMAC/s when clocked at 300MHz. “Traditionally there has been no one DSP that addresses both the high-end and the low power, high code density markets,” said Thomas Brooks, StarCore’s marketing director. The 16-bit SC140, the first member of the SC100 family, is designed to tackle both. To increase code density the core uses a variable instruction length scheme. Single 16-bit instructions are used for control functions, which make up the bulk of the code, while combining up to six instructions per clock cycle for the short but critical inner loops. StarCore claims this results in code densities approaching that of the ARM7 Thumb. It is also programmable in C, making the SC140 “the first compilable DSP for mobile phone handsets”, said Brooks. Asked why the SC140 is needed when current handsets require a 100Mips DSP, Brooks said: “Operating the SC140 at a lower voltage [0.9V] and 120MHz, the 480MMAC/s may be enough for 2.5 and early third generation phones but a big discontinuity is coming.” He added: “For third generation handsets to run GPS and full video sequences, thousands of Mips will be need.” First IC samples including the core and memory will be available in the fourth quarter. System ICs from Lucent and Motorola using the core will first appear by mid-2000. Besides mobile handsets, the other “candidate” applications for the core are basestations and ADSL, said Brooks.


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