SyncLink DRAM delay

SyncLink DRAM delay
David Manners
SyncLink DRAMs will be later than expected. The first full-scale chips were due from Micron Technology in the first quarter of 1998 and from Siemens in the second half.
“We’re roughly on schedule,” Jeff Maioloux, DRAM marketing manager at Micron told EW. “We’re in the debug process right now – it’s a very complicated part.” Maioloux reckons that Micron will have samples in the second quarter.
Micron’s chip will be a 200MHz 16-bit wide part, delivering 400Mbit/s per pin transfer rates for a total bandwidth of 800Mbyte/s. Micron’s project for Direct Rambus, the latest DRAM for Rambus’ competing micro/ memory interface, started much later than the SyncLink programme.
“We expect samples of Direct Rambus (which offers a total 1.6Gbyte/s bandwidth) either late this year or early next year,” said Maioloux.


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