Synopsys gets physical with chip design times

Synopsys gets physical with chip design timesRichard Ball  
 
It’s as important to chip designers as the first logic synthesis tool was on its introduction ten years ago. So claims Synopsys at the launch of ‘physical synthesis’, a brand new method of designing chips.
But what problems do physical synthesis and the first tool called Chip Architect address? Just what is all the fuss about?
“The problem can be characterised by two words – timing closure,” explained Aart de Geus, CEO of Synopsys. What’s the ‘iteration’ problem?
One of the major problems facing chip designers – mainly those working with cutting edge design processes such as 0.25?m and below – is that of design iterations.
The design flow for an Asic or custom IC has two major parts; synthesis followed by place-and-route. After synthesis, turning a hardware description language (HDL) into gates, the gates are placed on the chip and individual transistors are linked with metal (routed).
Only then can the actual speed of the chip can be predicted (with high accuracy). The timings and delays are back annotated to the HDL which almost always shows up problems – your 200MHz super-fandango chip limps along at 33MHz. Changes are made to the HDL and the whole process starts again (an iteration).
Various companies have said that recent designs needed 20 or more iterations around this loop. This, to put it mildly, takes shed loads of time and costs a king’s ransom. Anything that reduces the number of iterations is a good thing.  
 
Today, chip designers are always aiming for this ‘timing closure’ – the point where the final chip timing meets the specification. The quicker this is achieved, with as few design iterations as possible, the better (see boxout).
“Chip Architect allows you to achieve timing closure much more quickly,” said Bernie Mortell, technical marketing manager at Synopsys.
It does this by bringing some placement and routing technology into the synthesis part of the design process.
The approach starts with a normal top-down design flow and adds in physical information as early as possible to improve the quality of timing, area and power predictions.
The design flow has been split into several sections by Synopsys; black box planning, RTLplanning, gate level planning and final routing.
At the first level, very little physical information is available. But a top level router can calculate delays across the chip from early layouts of the blocks of the design. Predictions of timing are no better than 50 per cent accurate, Mortell said.
At the register transfer level, the code for the hardware blocks has been written. A fast synthesis step can be done and this halves the error in timing and delays.
After synthesis of the design, turning HDL code into gates, timing is 95 per cent accurate, Mortell said. In order to get to this level, the components of the chip must be placed, which is why Synopsys has created its own placement engine.
And this is why Synopsys is calling the new design flow physical synthesis.
“We think this opens up a whole new decade of design,” said deGeus.


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