Synopsys on hierarchical layout verification route

Synopsys on hierarchical layout verification routeRichard Ball
Synopsys has unveiled Cedar, a tool aimed at full chip physical layout verification.
This verification, involving design rule checking and layout versus schematic comparison is, at present, dominated by Cadence and Mentor Graphics.
This announcement is another example of Synopsys slowly working its way into new markets.
Cedar is aimed at bringing design reuse to physical verification by using a hierarchical approach as opposed to a flat model.
“Flat is where most people are at today. They are comfortable with this,” said Rick Nordin, product marketing manager at Synopsys.
But the use of intellectual property is convincing many designers to switch to some form of hierarchical approach.
This has the great advantage, when using Cedar, that once a block has been checked, it does not need to be rechecked after changes have been made elsewhere.
If a block itself is changed, then only that block needs to have the design rules checked.
“This eliminates any redundant checking and it’s easier to implement changes to a block or routing between blocks,” said Nordin. The time saving could amount to weeks or even months, he claimed.
Synopsys has also added a facility to let Cedar run across a network of multiple workstations.
A four machine network can reduce runtime by 66 per cent. Increasing the number of nodes can improve speed by up to 500 per cent, claimed Nordin.

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