Synopsys tools up for layout

Synopsys tools up for layout
Richard Ball Synopsys has announced its first chip design tool to include layout capability, bringing the company into the sector dominated by Cadence and Avant!. “We are defining a new flow and new set of tools,” Raul Camposano, chief technology officer at Synopsys told Electronics Weekly. “Chip Architect is what we call a design planner.” Chip Architect allows designers to account for physical effects early in a design. By increasing the predictability of a chip’s performance, Synopsys hopes to reduce design times. The tool links logical design, turning hardware description language into gates, with physical design, placing and routeing the gates onto the chip. It combines Design Compiler, Synopsys’ leading synthesis tool, with timing and power analysis, placement and top level routeing. The firm is calling this physical synthesis. For designers, Chip Architect brings the ability to analyse physical effects before the real layout is started. This will be useful as intellectual property (IP), in the form of a hardware description language, becomes more popular. IP can be quickly evaluated, measuring speed and power, to assess its suitability in a particular design. A fast synthesis step allows the timing of the design to be measured with 20 per cent accuracy, Camposano claimed. “At 0.25 to 0.18?m, this is a tremendous process,” he added. Camposano would not comment whether Synopsys would be extending the tool to include general chip routeing. This would be needed to break Cadence’s and Avant!’s hold on the market.


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