Synplicity tool eases design

Synplicity tool eases designRichard Ball Synplicity has extended its synthesis software for programmable logic designs with floorplanning and partitioning tools. These aim to reduce the time spent by the place and route tool, and speed the design cycle. “Newer FPGAs are really beginning to push the design methodology and it’s starting to break down,” said product manager Jeff Garrison. “Wiring delays are becoming significant, as with Asics.” The bottleneck in the design flow, says Garrison, is not with synthesis, but at the place and route stage of the design. Therefore Synplicity has taken part of that process, namely the floorplanning, and integrated it with the synthesis process. The engineer can manually place important blocks of the design and the tool gives hints to the FPGA place and route tool. “This makes the whole runtime much quicker,” said Garrison, up to 35 per cent in some instances. “We’ve also seen up to 20 per cent faster circuits,” he said. The partitioning tool also integrates with Synplify, the company’s synthesis tool. It allows engineers to take a large design and spread it across several FPGAs, useful for prototyping. “A big area in consumer electronics is rapid prototyping of large systems,” said Garrison.
The tool is not automatic, but uses the designers knowledge of the circuit to split it across the devices. It then gives feedback on utilisation and speed.

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