Synplicity tool targets faster Asic prototypes

Synplicity tool targets faster Asic prototypesRichard Ball
Synplicity has announced a tool aimed at improving the way a design is split among several programmable logic chips when prototyping Asic designs.
Called Certify, the tool combines synthesis and a partitioning technology. Updates to Synplify
Changes have also been made to Synplify, the firm’s synthesis tool, to take account of new FPGA architectures.
“We have substantial new improvements to take advantage of the features in Virtex, Xilinx’s new architecture,” said Haines.
Newly supported are Atmel’s 40K series and Dynachip’s DY6000 family. Apex, the million gate family from Altera, will be supported soon, Haines said.
Synplicity is a fast growing EDA firm. “We’ve doubled in head count in the last year,” said Haines. Revenue, he said, is following a similar trend. “This will position us for a public offering next year.”  
“The whole point of this is faster Asic prototypes,” said Andy Haines, vice-president of marketing at Synplicity.
Certify will allow designers to map their creation into a bank of FPGAs in a shorter time. The final prototype will run faster than competing technologies, such as emulation, claimed Haines.
According to Haines, there are several reasons why Asic prototypes, in the form of FPGA boards, will find more use in the coming years.
“Asics are increasingly using processors, so you have this hardware/software development cycle,” he said. “And with more graphics and audio application, designers need some real time verification.”
Prototyping can be cheaper than other techniques such as hardware emulation, but spreading an Asic design across multiple FPGAs can be difficult.
Larger FPGAs, such as Xilinx’s Virtex and Altera’s Apex, help alleviate the problems by fitting more of the Asic design into a single FPGA.
Synplicity’s new Certify tool helps further, by improving the way the design is split, or partitioned, across several devices.
The output of Certify can also be mapped directly into the prototyping system from Aptix (see p24). This typically runs at speeds of 10 to 20MHz, allowing complex applications, including graphics processors, to run at something approaching real time. Emulators typically run at around 1MHz.

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