Threaded processor design promises smaller, faster ICs

Threaded processor design promises smaller, faster ICsRichard Ball  
A US start-up has come up with a novel design for embedded microprocessors that promises smaller, faster ICs.
TeraGen has invented an architecture it calls thread processor technology. Several simple processing units called microthread engines (see diagram) are placed on a chip. In parallel, these can replicate the functions of existing processor architectures.
“What we’re developing is a technology that’s a flexible way of creating processors,” George Alexy, president and CEOof TeraGen told Electronics Weekly.
On-chip software or microcode, held in a ROM, converts conventional processor instructions into primitive operations for the microthread engine.
“We describe the architecture we’re implementing in the underlying microcode,” said Alexy.
This means that it is conceivable that any existing processor instruction set could be emulated by the microthread engines. This could cover eight to 32-bit processors. Architecture
Efficient pipeline
Superscalar + out of order and branch prediction
Thread processor Instructions/cycle
0.7 – 0.9
1.2 – 1.3
1.6 – 1.7
Scalable at 90 per cent efficiency for each
0.9 at one thread, 1.8 for two, etc. TeraGen’s thread processor addresses a problem facing microprocessor designers; more exotic techniques, such as out-of-order execution and superscalar architectures, use more transistors while offering non-linear performance increases. Performance increases with the square root of the number of transistors. Microthreads scale linearly, claims TeraGen.
And because each engine and its set of primitive operations are very simple, they will run very fast, easily over 200MHz in a 0.5?m process, Alexy said.
“The first platform that we are targeting is an eight bit microprocessor,” Alexy said. More specifically it is the 8051, still used in vast numbers today. At the speeds needed by 8051 designs, the chip will draw little current.  
  Thread bare… The thread processor gets its name because it takes processor instructions and breaks them down into multiple threads. Each thread is executed by an engine. The multiple engines are under the control of a real time operating system.
The devices are also small, Alexy claims.”Because of the characteristics of the design, it’s heavily ROM, datapath and RAM oriented. These are very dense which leads to small, high performance die,” he pointed out.
As the microthread engines can emulate pretty much anything, they will also be used to emulate peripherals.
The only thing that changes the engine from emulating a processor or a peripheral is the microcode in the ROM. This allows for a simple chip layout.
Development times, cost and chip size could all be reduced by up to 40 per cent, the company claims.
TeraGen chips could replace older processors in existing designs and re-use the existing code without changes.
Applications such as mobile phones, where the chip includes a CPU, DSPand peripherals could also be targeted.
In the future, Alexy said microcode could also be implemented in RAM, making the engines reconfigurable.
TeraGen will be licensing the technology to semiconductor companies as well as designing its own chips. “We have two licences at this time with semiconductor companies,” said Alexy.
The first 8051-compatible product is due sometime this year.

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