Three technologies in search of the mainstream

Three technologies in search of the mainstreamDavid Manners looks at the prospects of three technologies which are beginning to emerge into the commercial arena Silicon Germanium
For nearly twenty years SiGe research has been pursued as a way of boosting silicon frequencies to the level of gallium arsenide frequencies while retaining the low cost of silicon.
Bell Labs, IBM, Daimler-Benz and Stanford University have been the main research bodies involved in solving the basic SiGe problem – how to interface a germanium atom to a silicon atom when the former is four per cent larger than the latter.
If you add too much germanium, with its larger lattice spacing, to silicon, the silicon falls apart. These issues are now resolved.
Last year, IBM’s SiGe partner, the Canadian National Research Council, spun off a subsidiary – SiGe Microsystems – to commercialise the technology.
This year, IBM licensed its SiGe process to Nortel, Harris, Hughes, Tektronix and National Semiconductor.
IBM’s recent takeover of specialist GSM design house CommQuest is thought to presage development of a single-(SiGe)chip telephone.
Daimler-Benz commercialised SiGe technology through its chip-making subsidiary Temic which was bought this year by Atmel. Temic has three SiGe chips: a front end amplifier RF chip for DECT cordless phones, a low-noise amplifier for GSM and dual band handsets, and a power amplifier which does not need a negative supply voltage or a high side switch.
Analog Devices, Philips, NEC, Maxim, Siemens and M/A-COM are all said to be preparing SiGe products for the market. Silicon on Insulator
SOI – defined as a silicon layer coupled to an electrically insulating layer – delivers lower power devices.
It is especially efficacious as supply voltages drop to sub-1V levels, which is only a couple of years away for some consumer products like mobile phones.
SOI’s low power capability makes it the ideal technology for chips which are increasingly required by today’s portable, battery-powered electronics products.
Moreover, SOI’s advantages let you jump the generation gap – you can pack as many transistors into the same space with the previous generation of technology as you can with the present generation technology.
So, if it’s so great, why doesn’t everyone use it?
The main reason, up to now, has been the high cost of the raw SOI wafer, but ‘thin oxide SIMOX’ and the new ‘UNIBOND smart cut’ concepts, have improved defect density and wafer cost by an order of magnitude compared to the old ‘thick oxide SIMOX’ approach.
Now people are anticipating a time when the extra cost of SOI will be outweighed by SOI’s ability to deliver increased transistor density and low power.
Some people even expect to see the cost of SOI reduce to that of conventional bulk CMOS wafers.
Some people go so far as to claim that the die-cost of SOI is already equivalent to the die-cost of bulk CMOS.
Other people see SOI as becoming mainstream at the sub-1V, 0.1 micron level where it could deliver the isolation required to put RF, baseband processing, analog, and DSP all on one chip to produce single-chip telephones.
Yet another faction believes that SOI will always be a niche technology for rad-hard and ultra low power applications.
Despite being researched for over twenty years, SOI’s ultimate usefulness is is still in the lap of the Gods. Copper Interconnect
With increasing chip layers and longer interconnects, interconnect delay has been an increasing problem in chip manufacturing.
One solution is the replacement of the present aluminium interconnect with copper interconnect because copper has 40 per cent lower resistivity than aluminium.
Besides lower resistance, copper has the advantage of higher electromigration resistance, better step coverage, and can be deposited at lower temperatures than are needed for aluminium.
On the downside, copper is more difficult to etch than aluminium, it is vulnerable to scratching and corrosion, and it is poisonous to silicon – requiring barrier metals.
Sematech produced the world’s first copper interconnect wafer (in August 1997), and IBM produced the world’s first copper interconnect chip – a 480MHz PowerPC – shown at the 1998 ISSCC.
Sematech reckons that a 14 layer process can be reduced by 2 layers using copper and, if low-K (low dielectric constant) insulating materials are also used, a five or six layer reduction can be realised.
IBM estimated that using copper rather than aluminium in its ISSCC PowerPC added 27 per cent to the frequency, made a 12 per cent improvement to the path delay, and reduced clock latency from 170ps to 85ps.
Other companies expected to demonstrate a copper capability for roll-out in products this year or next are: Intel, TI, VLSI Technology, LSI Logic and Motorola.
Late last year production equipment manufacturer Applied Materials launched a system called Endura Electra Cu for depositing the barrier and seed layers for copper interconnect.


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