ARM launches new microarchitecture – DynamIQ

ARM has introduced a new microarchitecture for its Cortex-A series called DynamIQ.


DynamIQ allows up to eight cores to be put on a chip with different configurations like 1+7 (i.e. 1xbig and 7xLITTLE CPUs), 2+4, 1+3 to deliver scalable solutions

The first phones using DynamIQ will be out early in 2018.

DynamIQ aims to allow on-chip processing of AI applications. Dedicated instructions for AI and optimised libraries will speed up AI applications processing by 50x, claims ARM.

DynamIQ allows SoC designers to scale up to eight cores in a single cluster and each core can have different performance and power characteristics.

The new microarchitecture permits performance within restricted thermal budgets: Efficient and much faster switching of software tasks to match the right-sized processor for optimal performance and power is further enhanced through independent frequency control of individual processors

DynamIQ brings greater levels of responsiveness for ADAS solution and increased safety capabilities which will enable partners to build ASIL-D compliant systems for safe operation under failure conditions.

DynamIQ supports multiple, configurable, performance domains within a single cluster. These domains, consisting of single or multiple ARM CPUs, can scale in performance and power with finer granularity than previous quad-core clusters.

This means more fine-tuned ability to stay within the thermal envelope, which results in longer periods of sustained performance. This is especially critical in Virtual Reality (VR) applications, which require sustained performance over longer periods of time, in a thin device with limited battery life and heat thresholds.

DynamIQ technology also introduces a more rapid and autonomous hardware-controlled power state transition mechanism that reduces the latency between the power states supported by ARM Cortex-A CPUs (e.g. ON, OFF and SLEEP). This not only results in shorter durations for powering up a CPU and quicker response times, but also higher energy savings with quicker entry to power-saving states, such as sleep mode and power off.

Autonomous CPU memory power management, a way to intelligently adapt to the amount of local memory available to the CPUs depending on the type of application running, is another key feature in the technology. Applications that demand a high amount of compute performance, such as Augmented Reality (AR), will have the maximum amount of local memory at its dispense, while lighter applications, such as music streaming, will have a scaled-back amount of local memory, saving CPU memory power.

It is possible with a DynamIQ cluster to build both high performance ‘big’ CPUs and high efficiency ‘LITTLE’ CPUs into a single cluster with a shared coherent memory. In doing so, it not only delivers significant improvements in performance gained from a tighter, more coherent system, but it also presents unprecedented flexibility and choice in CPU cluster design to deliver purpose-built solutions.

Each CPU can scale at different frequencies for customized solutions frpm thin devices all the way to servers.

This will especially benefit homogeneous processing systems, such as networking, enabling higher data throughput with eight fully-coherent CPUs in a single cluster. When deployed with ARM CoreLink CMN-600 DynamIQ will scale to high-count multi-cluster systems for infrastructure markets.

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