Whereas a PLL is traditionally one of the major power consumers in a radio and can take up to 30% of the radio area, this ADPLL is 0.18mm² in 40nm CMOS with 0.67mW power consumption.
With all spurs lower than -56dBc and jitter below 2ps, it is robust.
The intuitive IoT relies on tiny sensor nodes, invisibly embedded in our environment and wirelessly connected to the internet. Battery replacement becomes impossible and therefore, power consumption reduction, especially in wireless connectivity, is the leading concern and challenge to address.
The PLL is the radio component for frequency synthesis and has traditionally been an analog component, although the research community has been working on digital alternatives. All-digital PLLs enable a smaller footprint, better control and testability, and improved scaling to advanced CMOS nodes. However, to-date, they have lagged behind in terms of performance, compared to analog solutions.
The PLL supports all specifications of Bluetooth Low Energy (BLE) radios while significantly reducing cost and power.
This divider less fractional-N digital PLL features a power-efficient spur-mitigation technique and a digital phase unwrap technique.
See also: Imec makes plastic NFC chip