“Die cost reduction has been enabled so far by concurrent scaling of poly pitch, metal pitch, and cell height scaling,” says IRDS concluding that this will likely continue until 2024.
After 2024, says the IRDS: There is no room for contact placement as well as worsening performance as a result of contacted poly pitch (CPP) scaling. It is projected that physical channel length would saturate around 12nm due to worsening electrostatics while CPP would saturate at 24nm to reserve sufficient CD (~11nm) for the device contact providing acceptable parasitics.”
FinFETs “could sustain scaling until 2021 for high-performance logic applications,” says IRDA, “beyond 2019 a transition to gate-all-around will start and potentially a transition to vertical nanowires devices will be needed when there will be no room left for gate length scale down due to the limits of fin width scaling.”
IRDS considers the use of high mobility compounds to increase drive current.
“It is necessary to pursue 3D integration routes such as stacking and monolithic 3D (or sequential integration) to maintain system performance and power gains while maintaining the cost advantages,” says IRDS.