ISSCC: CMOS chip for 300GHz wireless

Hiroshima University and Panasonic have developed at a transmitter capable of over 10Gbit/s over multiple channels at around 300GHz.

Hiroshima University - ISSCC: CMOS chip for 300GHz wireless

Aggregate multi-channel data rate exceeds 100Gbit/s, and the transmitter was implemented as a silicon CMOS IC, it was revealed at the International Solid-State Circuit Conference (ISSCC) in San Francisco.

The transmitter covers the275 to 305GHz which, according to the University, is currently unallocated and is to be discussed at the World Radiocommunication Conference 2019 under the International Telecommunication Union Radiocommunication Sector.

The demonstration used quadrature amplitude modulation (QAM).

“Now THz wireless technology is armed with very wide bandwidths and QAM-capability. The use of QAM was a key to achieving 100Gbit/s at 300GHz,” said Professor Minoru Fujishima of Hiroshima.

“Today, we usually talk about wireless data-rates in megabits per second or gigabits per second. But I foresee we’ll soon be talking about terabits per second. That’s what THz wireless technology offers. Such extreme speeds are currently confined in optical fibers. I want to bring fiber-optic speeds out into the air, and we have taken an important step toward that goal.”

The research group plans to further develop 300GHz circuits including receivers, modulators and demodulators.

Read more ISSCC stories on Electronics Weekly »

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