Embedded World: Lauterbach and UltraSoC back RISC-V

Lauterbach and UltraSoC have added support for the RISC-V open-source processor architecture to their joint chip development and debug environment.

RISC-V logo

“Across the industry there is rising excitement about the emergence of RISC-V as an open source processor,” said UltraSoC CEO Rupert Baines. “This is especially significant in heterogeneous multi-core architectures: engineers want the choice to ‘mix and ‘match’ cores and freely choose the best design for each application.

“The use of heterogeneous architectures is growing rapidly, and the rise of RISC-V shows that more than ever, designers don’t want to be restricted in their architectural choices,” said Lauterbach general manager Stephan Lauterbach. “Our existing relationship with UltraSoC demonstrates the power of combining our respective sets of vendor-independent development tools, giving our customers the ability to choose both the IP they use in their chip, and the environment in which they develop and debug.”

Trace32 from Lauterbach is a set of modular development tools with integrated debug environments to support embedded microprocessor architectures with debug, trace and logic analyser capabilities. UltraSoC embeds monitoring and analytics hardware within an SoC, claiming that it is non-intrusive and performs at wire speed.

Both UltraSoC and Lauterbach are active members of the RISC-V Foundation.

Lauterbach announced Trace32 could debug SiFive’s E31 and E51 RISC-V Core IP in October. Also in 2017, UltraSoC developed a specification for processor trace and offered it for adoption by the RISC-V Foundation as part of the open source specification – there are trace encoders from both 32 and 64 bit designs.

UltraSoC and Lauterbach are exhibiting at Embedded World in Nuremberg (27 Feb – 1 Mar). Lauterbach in hall 4 stand 210, UltraSoC in hall 3A stand 419.

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