Fe-NAND To boost performance and scaling of NAND

NAND flash memory could be about to get a make-over. Fe-NAND, the invention of two Japanese academics, will provide huge performance benefits to NAND, and permit the scaling of NAND to well below its currently expected limits.

Ferroelectric gate FETs can dramatically improve the performance of NAND flash memory, according to Shigeki Sakai of the novel electron devices group, at the Nanoelectronics Research Institute of the National Institute of Advanced Industrial Science and Technology (AIST), Japan’s largest public research organisation, and Ken Takeuchi, associate professor of the Graduate School of Engineering at the University of Tokyo

The FeFET, the memory cell developed by Sakai and Takeuchi, can be programmed and erased 100m or more times and with programming voltage of less than 6V, whereas conventional NAND flash memory cells have ten thousand program/erase endurance cycles with approximately 20V programming voltage.

Whereas 30nm is widely assumed to be the minimum geometry to which traditional floating point NAND flash will scale, the FeFET can be shrunk to the 20nm and 10nm technology generations.

Using the FeFETs as memory cells in a ferroelectric NAND (Fe-NAND) flash memory will not only dramatically increase the number of program/erase endurance cycles, but also decrease the capacitance coupling noise between neighbouring memory cells due to the absence of floating gates, claim Sakai and Takeuchi.

The FeFET cell was developed using an approximately 10nm-thick high-permittivity dielectric Hf-Al-O film, 400nm-thick ferroelectric SrBi2Ta2O9 film, and then 200nm-thick platinum film were deposited in this order on a p-type Si semiconductor substrate using a pulsed-laser deposition technique.

The conditions of impurity doping to the channel area had been adjusted so that the threshold voltage was optimized for a NAND flash memory cell. The gate, source, drain and substrate electrodes were formed using the photolithography. And then, an n-channel FeFET with a metal-ferroelectric-insulator-semiconductor (MFIS) stacked gate structure was obtained.

Threshold voltages of the FeFET were measured after applying programme and erase voltage pulses with a variety of pulse widths. The result was that the pulses with high speed of 10 µs and low voltage of 6V worked enough for showing two distinguishable threshold voltages which corresponded to the two different memorized states.

The threshold voltages of the FeFET were also measured after applying program and erase disturb voltages which were the voltages inevitably applied on unselected cells at the same time that the selected cells were programmed and erased.

As a result, the appropriate voltage application conditions for the unselected cells to avoid memory errors by the program and erase disturbs were discovered.

Judging from the extrapolated lines drawn on the threshold-voltage retention curves of the program, erase, and program disturb operations, this n-channel FeFET was expected to retain the data for as long as ten years. In addition, the threshold voltages did not change significantly even after 100m voltage pulses of 10 µs and 6 V were applied for both data programming and erasing, indicating that the FeFET had more program/erase endurance cycles than 100m times.

Therefore, conclude Sakai and Takeuchi, Fe-NAND is expected to be a high-density, high-capacity nonvolatile memory suitable for the future 20-nm and 10-nm technology generations.


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