Key to this performance is a constantly-running background calibration technique that allows the ADC to process its input signal without interruption, while compensating for ageing, temperature sensitivity, package stress and PCB stress.
The chip uses ‘error modulation’ – measuring each sample twice after adding a different small deliberate error each time. The difference in output value can be analysed with knowledge of the input error to determine correction factors.
The error is added using capacitor ‘shuffling’, which would normally require exponential rise in capacitor count with bit count. However, and this is the major innovation in the chip, instead of one big segmented capacitor array, the firm has used multiple clusters of segmented capacitor arrays with a shuffler in each cluster to reduce capacitor count to a manageable level.
This form of background calibration is a convergent process.
After correction coefficients are cleared to zero (uncalibrated), the rms value of the coefficient errors settles to 0.25ppm within 100,000 samples. The convergence time constant is 16,000 samples regardless of the input signal.
In what is described as 0.18μm/0.5μm CMOS, excluding the necessary digital calibration engine, the total area of the ADC core is 4mm2. It consumes 12.9mW total and estimated power for the calibration engine is 6.8mW, suggesting a175.5dB fingure-of-merit (SNDR+10log(BW/power)), said Analog Devices.
At 1Msample/s and Vref=5V, dynamic range is 102.7dB, and SNDR (spurious-free dynamic range) is 101.5dB including signal and reference noise.
Power comes from 1.8V and a 5V rails, and a 2.5-5V reference is required.
ISSCC paper 14.7
A Signal-independent background-calibrating 20b 1MS/s SAR ADC with 0.3ppm INL
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