ISSCC: Novel gate drive improves GaN power transistor switching

GaN power transistors can shrink AC‑DC power supplies and cut losses but, to get the best out of them, their gate drive waveform needs careful attention.

ISSCC paper 24.2

As a German team pointed out at ISSCC, GaN transistors have a threshold voltage of ~1V, which makes them vulnerable to spurious turn‑on through the Miller capacitance, particularly when the GaN device is in the upper half of a bridge as the lower transistor turns on.

Negative bias on the gate can cure this but negative bias on the gate throughout the off period, according to researchers, increases reverse conduction losses if the device is being used to simulate the reverse body diode inherent in silicon mosfets when ‘off’.

So three‑level drive can be appropriate – positive for ‘on’, negative during the Miller spike, and zero to reduce reverse conduction losses for the rest of the ‘off’ period.

The team, from Reutlingen University and Leibniz University Hannover, is using a full-bridge of low-voltage transistors to drive the gate from 5V.

To keep the capacitors that hold gate drive energy small enough to be integrated on the chip, two 15V gate drivers are added with their own reservoir capacitors.

The higher voltage means, for the same energy (dielectric willing), the reservoir capacitors can be shrunk dramatically compared with a 5V capacitor. These capacitors, one per 15V supply, are switched into the GaN device gate (via the source in one case) via resonant inductors with precise timing to speed the switching transitions. “By integrating all capacitors, the presented work reduces the pin‑count as well as bond wires in the gate loop and provides more flexibility for the PCB and system design,” said the team.

Various charge pumps allow the chip to have several supply options, work with both low-side and high-side GaN transistors, and in two- and three‑level modes.

The gate driver IC was fabricated in a 0.18μm HV BiCMOS technology. A maximum gate charge of 11.6nC can be delivered and maximum gate drive currents are 1.5A (sourcing) and 1.3A (sinking). All capacitors and inductors are integrated.

The three-level driver also supports GaN gate injection transistors (GITs), where a regulator delivers mA-level current into the gate when the GaN device is on.

Transients of >80V/3ns were measured in GIT three-level mode switching a 100V 10A load.

ISSCC paper 24.2
A fully integrated three-level 11.6nc gate driver supporting GaN gate injection transistors

ISSCC 2018
The IEEE’s annual International Solid-State Circuits Conference is the place where the world’s companies and universities gather to show off their chip-based circuit developments, and where attending engineers get a first glimpse of the state-of-the art in digital, analogue, power and RF design techniques.


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