Using very expensive accelerometers and gyros and integration, if you are a nuclear submarine.
But what if you are a pedestrian?
Revealed at the IEEE’s annual International Solid-State Circuits Conference in San Francisco this week was a dead-reckoner for walkers that fits in the heel of a shoe, and accumulates an error of only 5.5m after a 3.1km stroll.
It uses three-axis MEMS gyros and accelerometers – which would normally be far too drifty for navigation – enhanced by a shoe bottom-pressure sensor for drift and offset compensation.
The sensor is actually a 13×16 array of pressure sensing cells covering 54x54mm inside the heel, capable of delivering an ‘image’ of pressure as the heel is placed on the ground and the wearer moves above it, revealing not only that the heel has made contact with the ground, but how it made contact.
It is made from layers of polymer and conductors – much like a membrane keyboard in miniature. “A sensor pitch size of approximately 4x2mm is selected as a trade-off between the foot‑ground reaction sensing accuracy and array wiring complexity,” according to the paper on the technique presented at ISSCC 2018.
Instead of being a simple switch, inside each of the cells is an array of capacitive sensing electrodes that allow the magnitude of force to be measured as the cell is squashed. Nominal capacitance is 0.8pF, with a sensitivity of 3.7fF/kPa (up to 400kPa max).
Because 0.8pF is small compared to the capacitance of the array wiring and off-array connections, a set of invariant reference electrodes is also included in each cell to allow the effects of wiring to be nulled-out (Figure 1, above).
“Experimental results also reveal that the capacitive sensor is insensitive to inertial and vibration signals,” said the team, which has members from: University of Utah; University of California, Berkeley; Ozyegin University, Istanbul; and Case Western Reserve University.
Sensing is through a custom asic, fabricated at XFAB from 0.35μm CMOS, and is the main subject of the ISSCC paper. It scans the whole array every 10ms through a multiplexer – this is a trade-off between power dissipation and foot timing accuracy. To suit the chip to the broadest range of sensors, the internal capacitance‑to‑voltage converter has variable gain (1.5V-17.9V/pF) through offering a choice of both sense voltage and integration capacitor. The sensor has a dynamic range of 66dB (11-bit), which the chip matches. Chip output is 12-bit at 66.7ksample/s. Dissipation of the 10mm2 asic is 3mW.
Analysing data from the area sensor allows instantaneous pressure maps to be extracted, and the movement of the centre of pressure to be tracked across the array during movement.
The simplest way this data is used is to cease inertial measurement when the heel first strikes the ground, and resume it when the heel leaves the ground. As the heel is static when planted, velocity errors that accumulate while the heel is airborne can also be removed during each landing (done at mid landing time).
Further data fusion and navigation algorithms were employed to get the final 5m‑in‑3,100m accuracy.
ISSCC paper 10.2
Personal inertial navigation system employing mems wearable ground reaction sensor array and interface asic achieving a position accuracy of 5.5m over 3km walking distance without GPS
The IEEE’s annual International Solid-State Circuits Conference is the place where the world’s companies and universities gather to show off their chip-based circuit developments, and where attending engineers get a first glimpse of the state-of-the‑art in digital, analogue, power and RF design techniques.
These categories continue to blur as 2018 reveals, for example, several on-die digital LDOs – low drop-out regulators – that provide power to parts of large digital chips using digital chopping techniques to keep voltage rails under control.
In low-power design, analogue processing is finding a niche, saving a few microamps compared with digital equivalents – for an example, see the Georgia Tech chip described on page 8, among the ISSCC papers Electronics Weekly has sampled this week.
Looking at big processors, this year Intel described its 28‑core 14nm server‑class CPU which has a two‑dimensional on‑die mesh interconnect for inter‑core communication, and AMD described its multi‑chip module approach to mitigate the slowing of process scaling. It has developed a 4.8 billion transistor chiplet with eight x86 cores which can be used on lots of one to four across mainstream PCs, high-end desktops and servers.
As clocking levels off and architectural improvements take the strain, IBM revealed a z14 processor that, on the same power as its predecessor, has 50% more L2 cache, twice as much L3 cache and 25% more cores, running 200MHz faster – at 5.2GHz – using micro-architecture changes to branch prediction, cache management, and cryptography.