Imagination adds MIPS cores

The MIPS P6600 is the next evolution of the MIPS P-class family, building on the 32-bit P5600 CPU.

The P6600 is the most balanced mainstream high-performance CPU choice, enabling multicore 64-bit SoCs for mobile, home entertainment, networking, automotive and more. Customers have already licensed the P6600 for applications including high-performance computing and advanced image and vision systems.

The MIPS M6200 and M6250 are the latest additions to Imagination’s M-class family processors for MCUs/MPUs, further broadening the M-class roadmap for high-performance deeply embedded designs in segments requiring higher performance and larger address space, including wired/wireless modems, GPU supervisor processors, flash and SSD controllers, packet processing, industrial and motor control, advanced voice processing and more.

All based on the MIPS Release 6 (r6) architecture, the products extend the range of Imagination’s solutions in the high-volume mainstream CPU IP market.

MIPS P6600 key features include:

• 64-bit MIPS Warrior CPU based on a 16-stage multi-issue Out-of-Order (OoO) pipeline implementation, delivering outstanding computational throughput and area efficiency
• Integrated 128-bit MIPS SIMD Architecture (MSA) support for efficient parallel processing of vector operations in multimedia applications
• Sophisticated branch prediction with fully associative Level 1 BTB (branch target buffer) and an improved Level 2 cache sub-system
• Full hardware virtualisation support and Imagination’s OmniShiel technologies for enhanced security and reliability.

MIPS M6200 MCU & M6250 MPU key features include:

• Low-power, compact 32-bit CPUs based on a six-stage pipeline implementation, enabling 30% higher frequencies versus the MIPS microAptiv CPU for similar implementations
• Integrated DSP and SIMD functionality to address signal processing requirements of such applications as industrial/motor control, voice processing
• Support for microMIPS r6 Instruction Set Architecture (ISA) for code compression and reduced memory footprint
• Data integrity features, including ECC and parity protection.

AMBA APB debug interface enabling JTAG, multi-core and mixed core debugging
M6200 MCU:

• Includes a memory controller for tightly coupled 64-bit Instruction/Data SRAM
• A memory protection unit enables program/data security.

The M6250 MPU includes a memory controller for Instruction/Data L1 cache and optional tightly coupled ScratchPad RAMs (SPRAMs), an MMU which supports virtual memory, enabling full support for Linux and other high level operating systems, 40-bit eXtended Physical Addressing (XPA) support and an AMBA AXI3 Bus Interface Unit.